1. Field of the Invention
The present invention relates to a semiconductor device, and a method of manufacturing the same, and more specifically to a semiconductor device comprising a vertical pnp (V-PNP) bipolar transistor, and a method of manufacturing such a semiconductor device.
2. Background Art
Recent semiconductor integrated circuits, for example, bipolar integrated circuits have a structure wherein both npn-bipolar transistors and vertical pnp-bipolar transistors are packaged together. Also as represented by a BiCMOS, various elements, such as npn-bipolar transistors, MOS transistors, and pnp-bipolar transistors may be packaged together on the same substrate to constitute one chip.
FIGS. 6 to 8 are schematic sectional views for illustrating the sequence of process steps of a method of manufacturing a conventional bipolar integrated circuit wherein an npn-bipolar transistor (NPN), an lateral pnp-bipolar transistor (L-PNP), and a vertical pnp-bipolar transistor (V-PNP) are packaged together. The configuration and manufacturing method of a conventional bipolar integrated circuit will be described below referring to FIGS. 6 to 8.
First, as shown in FIG. 6A, a silicon oxide film 102 of a thickness of about 6000 angstrom is formed on a p-type silicon semiconductor substrate 101, and an opening 102a is formed in the silicon oxide film 102 by photolithography followed by dry etching. Then, phosphorus (P) ions are implanted into the substrate 101 using the silicon oxide film 102 as a mask under the condition of an acceleration energy of 120 keV, and a dose of 5×1014/cm2,and the substrate 101 is subjected to heat treatment at a temperature of 1200° C. for 30 minutes. Thereby, a buried n−-type layer 103 is formed on the area where in V-PNP is to be formed.
Next, as shown in FIG. 6B, after the silicon oxide film 102 is removed, a silicon oxide film 104 of a thickness of about 6000 angstrom is formed on the surface of the p-type silicon semiconductor substrate 101, and an opening is formed in the silicon oxide film 104 by photolithography followed by dry etching. Then, antimony (Sb) ions are implanted into the substrate 101 using the silicon oxide film 104 as a mask under the condition of an acceleration energy of 50 keV, and a dose of 4×1015/cm2, and the substrate 101 is subjected to heat treatment at a temperature of 1200° C. for 2 hours. Thereby, a buried n+-type layer 105 is formed on the area where an NPN and an L-PNP are to be formed.
Next, as shown in FIG. 6C, after the silicon oxide film 104 is removed, an underlying oxide film 106 of a thickness of about 1000 angstrom is formed, and a resist film 107 having a prescribed opening is formed by photolithography. Then, boron (B) ions are implanted into the substrate 101 using the resist film 107 as a mask under the condition of an acceleration energy of 50 keV, and a dose of 4×1014/cm2, and the substrate 101 is subjected to heat treatment at a temperature of 1000° C. for 30 minutes. Thereby, a lower isolation layer 119 for isolating NPN, L-PNP, and V-PNP regions from each other. In the region to form the V-PNP, a collector layer 120 consisting of the same layer as the lower isolation layer 119 is formed on the buried n−-type layer 103.
Next, as shown in FIG. 6D, after the resist film 107 and the underlying oxide film 106 are removed, epitaxial growth is performed. Thereby, an epitaxial layer 108 of a thickness of about 4 μm, and a resistivity of about 3 Ω·cm is formed on the p-type silicon semiconductor substrate 101.
Next, as shown in FIG. 7A, after a silicon nitride film (not shown) of a thickness of about 1000 angstrom is formed and patterned by photolithography followed by dry etching, the substrate 101 is subjected to heat treatment at a temperature of about 950° C. for about 3 hours to form a field oxide film 109 of a thickness of about 15000 angstrom on the epitaxial layer 108.
Next, as shown in FIG. 7B, an underlying oxide film 110 of a thickness of about 500 angstrom is formed on the epitaxial layer 108, and a resist film 111 having a prescribed opening is formed by photolithography. Thereafter, boron (B) ions are implanted using the resist film 111 as a mask under the condition of an acceleration energy of 50 keV, and a dose of 4×1014/cm2, and the substrate 101 is subjected to heat treatment at a temperature of 1000° C. for 30 minutes. Thereby, an upper isolation layer 121 connected to the lower isolation layer 119, and for isolating NPN, L-PNP, and V-PNP regions from each other together with the lower isolation layer 119, is formed. Also in the region to form the V-PNP, a collector contact layer 122 consisting of the same layer as the upper isolation layer 121 is formed, and connected to the collector layer 120.
In this step, instead of implanting boron ions, a boron-silicate glass (BSG) film may be deposited on the regions where these p-type diffused layers are to be formed, and subjected to heat treatment at about 800 to 1000° C., to diffuse boron in the boron-silicate glass into the epitaxial layer 108.
Next, as shown in FIG. 7C, after the resist film 111 is removed, a resist film 112 having a prescribed opening is formed by photolithography. Thereafter, boron ions are implanted using the resist film 112 as a mask under the condition of an acceleration energy of 50 keV, and a dose of 4×1014/cm2, and the substrate 101 is subjected to heat treatment at a temperature of 1000° C. for 15 minutes. Thereby, a base layer 124 is formed on the region to form the NPN, an emitter layer 123 is formed on the region to form the V-PNP, and a diffused layer 127 to be an emitter layer and a collector layer is formed on the region to form the L-PNP.
Next, as shown in FIG. 7D, after a silicon oxide film 113 is formed on the entire surface of the substrate 101, and the silicon oxide film 113 is selectively removed by photolithography followed by dry etching.
Next, as shown in FIG. 8A, a resist film 114 having a prescribed opening is formed by photolithography. Then, arsenic (As) ions are implanted using the resist film 114 as a mask under the condition of an acceleration energy of 50 keV, and a dose of 5×1015/cm2, and the substrate 101 is subjected to heat treatment at a temperature of 1000° C. for 20 minutes. Thereby, an emitter layer 125 is formed in the base layer 124 on the region to form the NPN, and a base-leader layer 126 connected to the epitaxial layer 108 as the base layer is formed on the region to form the V-PNP.
Next, as shown in FIG. 8B, an aluminum film 115 of a thickness of about 6500 angstrom to be a contact layer is formed, and an electrode consisting of the aluminum film 115 is formed by photolithography followed by dry etching.
Next, as shown in FIG. 8C, an interlayer insulating film 116 which consists of silicon oxide film of a thickness of about 10000 angstrom is formed, and a through-hole 116a that reaches the electrode consisting of the aluminum film 115 is formed by photolithography followed by dry etching.
Then, an aluminum film 117 of a thickness of about 10000 angstrom is formed and patterned by photolithography followed by dry etching. Thereafter, a glass coating film 118 of a thickness of about 7500 angstrom is formed, and a prescribed opening is formed by photolithography followed by dry etching. Thereby, the structure of a bipolar integrated circuit as shown in FIG. 8D is obtained.
However, in a conventional semiconductor device as shown in FIGS. 6 to 8, a buried n−-layer 103 different from other regions must be formed in the region to form a vertical pnp-bipolar transistor on a p-type silicon semiconductor substrate 101.
Moreover, a buried N+-layer 105 must be formed in order to isolate the region other than the region to form the vertical pnp-bipolar transistor from the substrate potential, to use it as the collector layer of the npn-bipoler transistor, and to reduce the resistance of the collector layer. However, in the region to form the pnp-bipolar transistor, a p-type diffused layer, as the collector layer 120, cannot be formed directly on the buried N+-layer 105 formed to be same as other regions. The reason is that since the buried N+-layer 105 has a high concentration, the formation of the p-type diffused layer of the inverse conductivity type overlapping the buried N+-layer 105 is difficult. Therefore, as FIG. 6 shows, the collector layer 120 is formed after the deep buried n−-layer 103 of a low concentration is formed.
Although this buried n−-layer 103 has the function to isolate the collector layer 120 from the potential of the p-type silicon semiconductor substrate 101, process steps, such as the formation of the underlying silicon oxide film 102, photolithography followed by dry etching, the implantation of phosphorus ions, heat treatment, and the removal of the silicon oxide film 102, is essential for forming the buried n−-layer 103.
Therefore, problems of the complicated process steps, and increase in manufacturing costs arise. In addition, the buried n−-layer 103 must be aligned with the collector layer 120 at high accuracy, and dimensional margins of about 2 μm in the horizontal direction must be secured on the both side of the collector layer 120 to form the buried n−-layer 103. This is because the collector layer 120 cannot be isolated electrically from the p-type silicon semiconductor substrate 101, unless the buried n−-layer 103 is formed immediately under the collector layer 120. Therefore, increase in the area of the vertical pnp-bipolar transistor cannot be avoided.
In the conventional semiconductor devices, as described above, a buried n−-layer 103 different from other regions must be formed in the region to form a vertical pnp-bipolar transistor. This makes the process steps complicated, and results in increase in manufacturing costs. Also, since the buried n−-layer 103 must be accurately aligned to the collector layer 120, the region to form a vertical pnp-bipolar transistor is expanded in order to secure the dimensional margins.